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mt9m021/mt9m031: 1/3-inch cmos digital image sensor features mt9m021-mt9m031_ds rev. g pub. 4/15 en 1 ?semiconductor components industries, llc,2015 1/3-inch cmos digital image sensor mt9m021/mt9m031 datasheet, rev. g for the latest datasheet revision, please visit www.onsemi.com features ? superior low-light performance ? hd video (720p60) ? global shutter ? video/single frame mode ? flexible row-skip modes ? on-chip ae and statistics engine ? parallel and serial output ? support for external led or flash ? auto black level calibration ?context switching applications ? scene processing ? scanning and machine vision ? 720p60 video applications general description the on semiconductor mt9m021/mt9m031 is a 1/3- inch cmos digital image sens or with an active-pixel array of 1280h x 960v. it in cludes sophisticated camera functions such as auto exposure control, windowing, scaling, row skip mode, and both video and single frame modes. it is designed for low light performance and features a global shutter for accurate capture of moving scenes. it is programmable through a simple two-wire serial interface. the mt9m021/mt9m031 produces extraordinarily clear, sharp digital pictures, and its ability to capture both continuous video and single frames makes it the perfect choice for a wide range of applications, including scanning and hd video. table 1: key parameters parameter typical value optical format 1/3-inch (6 mm) active pixels 1280 x 960 = 1.2 mp pixel size 3.75 ? m color filter array rgb bayer or monochrome shutter type global shutter input clock range 6 C 50 mhz output pixel clock (maximum ) 74.25 mhz output serial hispi (ibga package only) parallel 12-bit frame rate full resolution 45 fps 720p 60 fps responsivity (monochrome) 6.1 v/lux-sec responsivity (color) 5.3 v/lux-sec snr max 38 db dynamic range 64 db supply voltage i/o 1.8 or 2.8 v digital 1.8 v analog 2.8 v hispi 0.4 v power consumption <400 mw operating temperature (ambient) C30c to +70c package options 9 x 9 mm 64-pin ibga 10x10mm 48-pin ilcc
mt9m021-mt9m031_ds rev. g pub. 4/15 en 2 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description mt9m021ia3xtc-dpbr 1.2 mp 1/3" gs cis dry pack with protective film, double side bbar glass mt9m021ia3xtc-drbr 1.2 mp 1/3" gs cis dry pack without protective film, double side bbar glass mt9m021ia3xtm-dpbr 1.2 mp 1/3" gs cis dry pack with protective film, double side bbar glass mt9m021ia3xtm-drbr 1.2 mp 1/3" gs cis dry pack without protective film, double side bbar glass mt9m021ia3xtmz-dpbr 1.2 mp 1/3" gs cis dry pack with protective film, double side bbar glass mt9m021ia3xtmz-drbr 1.2 mp 1/3" gs cis dry pack without protective film, double side bbar glass mt9m021ia3xtmz-tpbr 1.2 mp 1/3" gs cis tape & reel with protective film, double side bbar glass MT9M031D00STMC24BC1-200 1 mp 1/6" soc die sales, 200 ? m thickness mt9m031i12stc-dpbr 1 mp 1/6" soc dry pack with protective film, double side bbar glass mt9m031i12stc-drbr 1.2 mp 1/3" gs cis dry pack without protective film, double side bbar glass mt9m031i12stm-dpbr 1.2 mp 1/3" gs cis dry pack with protective film, double side bbar glass mt9m031i12stm-drbr 1.2 mp 1/3" gs cis dry pack without protective film, double side bbar glass mt9m031i12stmz-drbr 1.2 mp 1/3" gs cis dry pack without protective film, double side bbar glass
mt9m021-mt9m031_ds rev. g pub. 4/15 en 3 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor ordering information
mt9m021-mt9m031_ds rev. g pub. 4/15 en 4 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor ordering information
mt9m021-mt9m031_ds rev. g pub. 4/15 en 5 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 features overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 power-on reset and standby timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
mt9m021-mt9m031_ds rev. g pub. 4/15 en 6 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor list of figures list of figures figure 1: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 2: typical configuration: serial fo ur-lane hispi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 3: typical configuration: parallel pixel data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 4: 9x9mm 64-ball ibga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 5: 48 ilcc package, parallel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 6: two-wire serial bus timing para meters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 7: i/o timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 8: differential output voltage for clock or data pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 9: eye diagram for clock and data signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 10: skew within the phy and output channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 11: power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 12: power down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 13: quantum efficiency ? monochrome sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 14: quantum efficiency ? color sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 15: 64-ball ibga package outline dr awing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 16: 48-pin ilcc package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
mt9m021-mt9m031_ds rev. g pub. 4/15 en 7 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor list of tables list of tables table 1: key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin descriptions - 64-ball ibga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 4: pin descriptions - 48 ilcc package, parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 5: two-wire serial bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 6: i/o timing characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7: i/o rise slew rate (2.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 8: i/o fall slew rate (2.8v v dd _io) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 9: i/o rise slew rate (1.8v v dd _io) 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 10: i/o fall slew rate (1.8v v dd _io) 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 11: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 12: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 13: operating current consumption for parallel output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 14: standby current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 15: input voltage and current (hispi power supply 0.4 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 16: rise and fall times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 17: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 18: power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
mt9m021-mt9m031_ds rev. g pub. 4/15 en 8 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor general description general description the on semiconductor mt9m021/mt9m031 can be operated in its default mode or programmed for frame size, exposure, gain , and other parameters. the default mode output is a full-resolut ion image at 45 frames per second (fps). it outputs 12-bit raw data, using either the parallel or serial (hispi) ou tput ports. the device may be operated in video (master) mode or in frame trigger mode. frame_valid and line_valid signals are output on dedicated pins, along with a synchronized pixel clock. a dedicated flash pin can be programmed to control external led or flash exposure illumination. the mt9m021/mt9m031 includes additional fe atures to allow application-specific tuning: windowing, adjustable auto-exposur e control, auto black level correction, on-board temperature sensor, and ro w skip and digital binning modes. the sensor is designed to operate in a wide temperature range (?30c to +70c). functional overview the mt9m021/mt9m031 is a progressive-scan se nsor that generates a stream of pixel data at a constant frame rate. it uses an on -chip, phase-locked loop (pll) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 50 mhz. the maximum output pixel rate is 74.25 mp/s, corre- sponding to a clock rate of 74.25 mhz. figu re 1 shows a block diagram of the sensor. figure 1: block diagram user interaction with the sensor is through the two-wire serial bus, which communi- cates with the array control, analog signal chai n, and digital signal chain. the core of the sensor is a 1.2 mp active- pixel sensor ar ray. the mt9m021/mt9m031 features global shutter technology for accurate capture of moving images. the exposure of the entire array is controlled by programming the integr ation time by register setting. all rows simultaneously integrate light prior to readout. once a row has been read, the data from the columns is sequenced through an analog signal chain (providing offset correction and gain), and then through an analog-to- digital converter (adc). the output from the adc is a 12-bit value for each pixel in the array. the adc output passes through a digital control registers active pixel sensor (aps) array pll memory otpm temperature sensor timing and control (sequencer) analog processing and a/d conversion auto exposure and stats engine pixel data path (signal processing) external clock serial output flash parallel output two-wire serial interface trigger power
mt9m021-mt9m031_ds rev. g pub. 4/15 en 9 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor features overview processing signal chain (which provides furt her data path corrections and applies digital gain). the pixel data are output at a rate of up to 74.25 mp/s, in parallel to frame and line synchronization signals. features overview the mt9m021/mt9m031 global sensor shutter ha s a wide array of features to enhance functionality and to increase versatility. a su mmary of features follows. please refer to the mt9m021/mt9m031 developer guide for de tailed feature descriptions, register settings, and tuning guidelines and recommendations. ?operating modes the mt9m021/mt9m031 works in master (video ), trigger (single frame), or auto trig- ger modes. in master mode, the sensor generates the integration and readout timing. in trigger mode, it accepts an external tr igger to start exposure, then generates the exposure and readout timing. the exposu re time is programmed through the two- wire serial interface for both modes. note: trigger mode is not compatible with the hispi interface. ?window control configurable window size and blanking ti mes allow a wide range of resolutions and frame rates. digital binning and skipping modes are supported, as are vertical and horizontal mirror operations. ?context switching context switching may be used to rapidly switch between two sets of register values. refer to the mt9m021/mt9m031 develope r guide for a complete set of context switchable registers. ?gain the mt9m021/mt9m031 global shutter sensor can be configured for analog gain of up to 8x, and digital gain of up to 8x. ?automatic exposure control the integrated automatic exposure control may be used to ensure optimal settings of exposure and gain are computed and updated every other frame. refer to the mt9m021/mt9m031 developer guide for more details. ?hispi the mt9m021/mt9m031 global shutter image sensor supports two or three lanes of streaming-sp or packetized-sp protocols of on semiconductor's high-speed serial pixel interface. ?pll an on chip pll provides reference clock flexibility and supports spread spectrum sources for improved emi performance. ?reset the mt9m021/mt9m031 may be reset by a register write, or by a dedicated input pin. ?output enable the mt9m021/mt9m031 output pins may be tri-stated using a dedicated output enable pin. ?temperature sensor ? black level correction ?row noise correction ? column correction ? test patterns several test patterns may be enabled for debug purposes. these include a solid color, color bar, fade to grey, and a walking 1s test pattern.
mt9m021-mt9m031_ds rev. g pub. 4/15 en 10 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor features overview figure 2: typical configuration: serial four-lane hispi interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but it may be greater for slower two-wire speed. 3. this pull-up resistor is not required if the contro ller drives a valid logic level on sclk at all times. 4. the parallel interface output pads can be left un connected if the serial output interface is used. 5. on semiconductor recommends that 0.1f and 10f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. refer to the mt 9m021/mt9m031 demo headboard schematics for circuit recommendations. 6. on semiconductor recommends that analog powe r planes be placed in a manner such that cou- pling with the digital power planes is minimized. 7. although 4 serial lanes are shown, the mt9m021/mt9m031 supports only 2 or 3 lane hispi. v dd _io v dd _slvs v dd _pll v dd v aa v dd v aa v aa _pix master clock (6C50 mhz) s data sclk reset_bar test extclk d gnd a gnd digital ground analog ground digital core power 1 hispi power 1 analog power 1 to controller from controller v dd _io v dd _pll pll power 1 digital i/o power 1 1.5k 2 1.5k 2, 3 analog power 1 v aa _pix slvsc_n slvsc_p slvs0_p slvs0_n slvs1_p slvs1_n slvs2_p slvs2_n slvs3_p slvs3_n flash v dd _slvs oe_bar standby
mt9m021-mt9m031_ds rev. g pub. 4/15 en 11 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor features overview figure 3: typical configuration: parallel pixel data interface notes: 1. all power supplies mu st be adequately decoupled. 2. on semiconductor recommends a resistor value of 1.5k ? , but it may be greater for slower two-wire speed. 3. this pull-up resistor is not required if the contro ller drives a valid logic level on sclk at all times. 4. the serial interface output pads can be left un connected if the parallel ou tput interface is used. 5. on semiconductor recommends that 0.1f and 10f decoupling capacitors for each power supply are mounted as close as possible to the pad. actu al values and results may vary depending on lay- out and design considerations. refer to the mt 9m021/mt9m031 demo headboard schematics for circuit recommendations. 6. on semiconductor recommends that analog powe r planes be placed in a manner such that cou- pling with the digital power planes is minimized. v dd master clock (6C50 mhz) s data sclk test flash frame_valid d out [11:0] extclk d gnd digital ground analog ground digital core power 1 to controller from controller line_valid pixclk reset_bar v dd _io digital i/o power 1 1.5k 2 1.5k 2, 3 v aa vaa_pix analog power 1 vdd_pll pll power 1 analog power 1 vaa_pix v dd _io v dd _pll v dd v aa trigger oe_bar standby a gnd
mt9m021-mt9m031_ds rev. g pub. 4/15 en 12 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor features overview figure 4: 9x9mm 64-ball ibga package a b c d e f g h top view (ball down) slvs0n slvs0p slvs1n slvs1p v dd standby vdd_pll slvscn slvscp slvs2n slvs2p v dd v aa v aa extclk v dd _ slvs slvs3n slvs3p d gnd v dd agnd agnd s addr sclk s data d gnd d gnd v dd vaa_pix vaa_pix line_ valid frame_ valid pixclk flash d gnd v dd _io reserved d out 8 d out 9d out 10 d out 11 d gnd test d out 4 d out 5d out 6d out 7 d gnd trigger oe_bar d out 0 d out 1 d out 2d out 3d gnd reset _bar 12 3 567 8 4 v dd v dd _io v dd _io v dd _io v dd _io reserved reserved
mt9m021-mt9m031_ds rev. g pub. 4/15 en 13 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor features overview table 3: pin descriptions - 64-ball ibga package name ibga pin type description slvs0_n a2 output hispi serial data, lane 0, differential n. slvs0_p a3 output hispi serial data, lane 0, differential p. slvs1_n a4 output hispi serial data, lane 1, differential n. slvs1_p a5 output hispi serial data, lane 1, differential p. standby a8 input standby-mode enable pin (active high). vdd_pll b1 power pll power. slvsc_n b2 output hispi serial ddr clock differential n. slvsc_p b3 output hispi serial ddr clock differential p. slvs2_n b4 output hispi serial data, lane 2, differential n. slvs2_p b5 output hispi serial data, lane 2, differential p. v aa b7, b8 power analog power. extclk c1 input external input clock. v dd _slvs c2 power hispi power. slvs3_n c3 output hispi serial data, lane 3, differential n. slvs3_p c4 output hispi serial data, lane 3, differential p. d gnd c5, d4, d5, e5, f5, g5, h5 power digital gnd. v dd a6, a7, b6, c6, d6 power digital power. a gnd c7, c8 power analog gnd. s addr d1 input two-wire serial address select. s clk d2 input two-wire serial clock input. s data d3 i/o two-wire serial data i/o. v aa _pix d7, d8 power pixel power. line_valid e1 output asserted when d out line data is valid. frame_valid e2 output asserted when d out frame data is valid. pixclk e3 output pixel clock out. d out is valid on rising edge of this clock. flash e4 output control signal to drive external light sources. v dd _io e6, f6, g6, h6, h7 power i/o supply power. d out 8 f1 output parallel pixel data output. d out 9 f2 output parallel pixel data output. d out 10 f3 output parallel pixel data output. d out 11 f4 output parallel pixel data output (msb) test f7 input manufacturing test enable pin (connect to d gnd ). d out 4 g1 output parallel pixel data output. d out 5 g2 output parallel pixel data output. d out 6 g3 output parallel pixel data output. d out 7 g4 output parallel pixel data output. trigger g7 input exposure synchronization input. oe_bar g8 input output enable (active low). d out 0 h1 output parallel pixel data output (lsb) d out 1 h2 output parallel pixel data output. d out 2 h3 output parallel pixel data output. d out 3 h4 output parallel pixel data output.
mt9m021-mt9m031_ds rev. g pub. 4/15 en 14 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor features overview figure 5: 48 ilcc package, parallel output reset_bar h8 input asynchronous reset (active low). all settings are restored to factory default. reserved e7, e8, f8 n/a reserved (do not connect). table 3: pin descriptions (continued)- 64-ball ibga package name ibga pin type description 6 5 4 3 2 1 48 47 46 45 44 43 d gnd extclk v dd _p ll d out 6 d gnd nc 7 d out 7 nc 42 8 d out 8 nc 41 9 d out 9 v aa 40 10 d out 10 a gnd 39 11 d out 11 v aa _pix 38 12 v dd _io v aa _pix 37 13 pixclk v aa 36 14 v dd a gnd 35 15 s clk v aa 34 16 s data reserved 33 17 reset _bar reserved 32 18 v dd _io reserved 31 v dd nc nc standby s addr test flash trigger frame_valid line_valid d gnd 19 20 21 22 23 24 25 26 27 28 29 30 d out 5 d out 4 d out 3 d out 2 d out 1 d out 0 oe_bar
mt9m021-mt9m031_ds rev. g pub. 4/15 en 15 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor features overview table 4: pin descriptions - 48 ilcc package, parallel pin number name type description 1d out 4 output parallel pixel data output. 2d out 5 output parallel pixel data output. 3d out 6 output parallel pixel data output. 4v dd _pll power pll power. 5 extclk input external input clock. 6d gnd power digital ground. 7d out 7 output parallel pixel data output. 8d out 8 output parallel pixel data output. 9d out 9 output parallel pixel data output. 10 d out 10 output parallel pixel data output. 11 d out 11 output parallel pixel data output (msb). 12 v dd _io power i/o supply power. 13 pixclk output pixel clock out. d out is valid on rising edge of this clock. 14 v dd power digital power. 15 s clk input two-wire serial clock input. 16 s data i/o two-wire serial data i/o. 17 reset_bar input asynchronous reset (active lo w). all settings are restored to factory default. 18 v dd _io power i/o supply power. 19 v dd power digital power. 20 nc no connection. 21 nc no connection. 22 standby input standby-mode enable pin (active high). 23 oe_bar input output enable (active low). 24 s addr input two-wire serial address select. 25 test input manufacturing test enable pin (connect to d gnd ). 26 flash output flash output control. 27 trigger input exposure synchronization input. 28 frame_valid output asserted when d out frame data is valid. 29 line_valid output asserted when d out line data is valid. 30 d gnd power digital ground 31 reserved n/a reserved (do not connect). 32 reserved n/a reserved (do not connect). 33 reserved n/a reserved (do not connect). 34 v aa power analog power. 35 a gnd power analog ground. 36 v aa power analog power. 37 v aa _pix power pixel power. 38 v aa _pix power pixel power. 39 a gnd power analog ground. 40 v aa power analog power. 41 nc no connection. 42 nc no connection.
mt9m021-mt9m031_ds rev. g pub. 4/15 en 16 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications electrical specifications unless otherwise stated, the following specif ications apply to the following conditions: v dd = 1.8v ? 0.10/+0.15; v dd _io = v dd _pll = v aa = v aa _pix = 2.8v 0.3v; v dd _slvs = 0.4v ? 0.1/+0.2; t a = -30 c to +70 c; output load = 10pf; pixclk frequency = 74.25 mhz; hispi off. two-wire serial register interface the electrical characteristics of the two-wire serial register interface (s clk , s data ) are shown in figure 6 and table 5. figure 6: two-wire serial bus timing parameters note: read sequence: for an 8-bit read, read waveforms start after write command and register address are issued. 43 nc no connection. 44 d gnd power digital ground. 45 d out 0 output parallel pixel data output (lsb) 46 d out 1 output parallel pixel data output. 47 d out 2 output parallel pixel data output. 48 d out 3 output parallel pixel data output. table 4: pin descriptions (continued)- 48 ilcc package, parallel pin number name type description s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f s data s clk p s t buf t r t f t r t hd;sta
mt9m021-mt9m031_ds rev. g pub. 4/15 en 17 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications notes: 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 27 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automa tically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. table 5: two-wire serial bus characteristics f extclk = 27 mhz; v dd = 1.8v; v dd _io = 2.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v; t a = 25c parameter symbol standard-mode fast-mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time: t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf serial interface input pin capacitance cin_si - 3.3 - 3.3 pf s data max load capacitance cload_sd - 30 - 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ?
mt9m021-mt9m031_ds rev. g pub. 4/15 en 18 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications i/o timing by default, the mt9m021/mt9m031 launches pixel data, fv and lv with the falling edge of pixclk. the expectation is that the user captures d out [11:0], fv and lv using the rising edge of pixclk. the launch edge of pixclk can be configured in register r0x3028. see figure 7 below and table 6 on page 18 for i/o timing (ac) characteristics. figure 7: i/o timing diagram table 6: i/o timing characteristics 1 parallel output symbol definition condition v dd _io=2.8v v dd _io=1.8v unit min typ max min typ max f extclk input clock frequency 6506 50mhz t extclk input clock period 20 166 20 166 ns t r input clock rise time pll enabled 34 34ns t f input clock fall time pll enabled 34 34ns t rp pixclk rise time slew setting = 4 (default) 2.3 4.6 2.3 4.6 ns t fp pixclk fall time slew setting = 4 (default) 3 4.4 3 4.4 ns pixclk duty cycle 40 50 60 40 50 60 % f pixclk pixclk frequency 2 nominal voltages, pll enabled 6 74.25 6 74.25 mhz t pd pixclk to data valid nominal voltages, pll enabled -3 2.3 4 -3 2.3 4.5 ns data[11:0] line_valid/ pixclk extclk t r t extclk t f frame_valid leads line_valid by 6 pixclks. frame_valid trails line_valid by 6 pixclks. t plh t pfh t pfl t pll t pd pxl _0 pxl _1 pxl _2 pxl _n 90% 10% t rp t fp 90% 10% frame_valid
mt9m021-mt9m031_ds rev. g pub. 4/15 en 19 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications notes: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70c ambient at 90% of v dd _io, and -30c at 110% of vdd_io. all values are taken at the 50% transition point. the loading used is 20pf. 2. jitter from pixclk is already taken into account as the data of all the output parameters. note: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70c ambient at 90% of v dd _io, and -30c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20pf. t pfh pixclk to fv high nominal voltages, pll enabled -3 1.5 4 -3 1.5 4.5 ns t plh pixclk to lv high nominal voltages, pll enabled -3 2.3 4 -3 2.3 4.5 ns t pfl pixclk to fv low nominal voltages, pll enabled -3 1.5 4 -3 1.5 4.5 ns t pll pixclk to lv low nominal voltages, pll enabled -3 2 4 -3 2 4.5 ns table 7: i/o rise slew rate (2.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 1.08 1.77 2.72 v/ns 6 default 0.77 1.26 1.94 v/ns 5 default 0.58 0.95 1.46 v/ns 4 default 0.44 0.70 1.08 v/ns 3 default 0.32 0.51 0.78 v/ns 2 default 0.23 0.37 0.56 v/ns 1 default 0.16 0.25 0.38 v/ns 0 default 0.10 0.15 0.22 v/ns table 6: i/o timing characteristics 1 (continued) parallel output symbol definition condition v dd _io=2.8v v dd _io=1.8v unit min typ max min typ max
mt9m021-mt9m031_ds rev. g pub. 4/15 en 20 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications note: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70c ambient at 90% of v dd _io, and -30c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20pf. note: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70c ambient at 90% of v dd _io, and -30c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20pf. notes: 1. minimum and maximum values are taken at the temperature and voltage limits; for instance, 70c ambient at 90% of v dd _io, and -30c at 110% of v dd _io. all values are taken at the 50% transition point. the loading used is 20pf. table 8: i/o fall slew rate (2.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 1.00 1.62 2.41 v/ns 6 default 0.76 1.24 1.88 v/ns 5 default 0.60 0.98 1.50 v/ns 4 default 0.46 0.75 1.16 v/ns 3 default 0.35 0.56 0.86 v/ns 2 default 0.25 0.40 0.61 v/ns 1 default 0.17 0.27 0.41 v/ns 0 default 0.11 0.16 0.24 v/ns table 9: i/o rise slew rate (1.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.41 0.65 1.10 v/ns 6 default 0.30 0.47 0.79 v/ns 5 default 0.24 0.37 0.61 v/ns 4 default 0.19 0.28 0.46 v/ns 3 default 0.14 0.21 0.34 v/ns 2 default 0.10 0.15 0.24 v/ns 1 default 0.07 0.10 0.16 v/ns 0 default 0.04 0.06 0.10 v/ns table 10: i/o fall slew rate (1.8v v dd _io) 1 parallel slew rate (r0x306e[15:13]) conditions min typ max units 7 default 0.42 0.68 1.11 v/ns 6 default 0.32 0.51 0.84 v/ns 5 default 0.26 0.41 0.67 v/ns 4 default 0.20 0.32 0.52 v/ns 3 default 0.16 0.24 0.39 v/ns 2 default 0.12 0.18 0.28 v/ns 1 default 0.08 0.12 0.19 v/ns 0 default 0.05 0.07 0.11 v/ns
mt9m021-mt9m031_ds rev. g pub. 4/15 en 21 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications dc electrical characteristics the dc electrical characteristics are show n in table 11, table 12, table 13, and table 14. caution stresses greater than those listed in table 12 may cause permanent damage to the device. this is a stress rating only, and functional ope ration of the device at these or any other con- ditions above those indicated in the operational sections of this specification is not implied. note: 1. exposure to absolute maximum rating condit ions for extended periods may affect reliability. note: 1. i dd _io operating current is specified wi th image at 1/2 saturation level. table 11: dc electrical characteristics symbol definition condition min typ max unit v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 1.7/2.5 1.8/2.8 1.9/3.1 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v dd _pll pll supply voltage 2.5 2.8 3.1 v v dd _slvs hispi supply voltage 0.3 0.4 0.6 v v ih input high voltage v dd _io * 0.7 C C v v il input low voltage CCv dd _io * 0.3 v i in input leakage current no pull-up resistor; v in = v dd _io or d gnd 20 C C ? a v oh output high voltage v dd _io C 0.3 C C v v ol output low voltage v dd _io = 2.8v C C 0.4 v i oh output high current at specified v oh C22 C C ma i ol output low current at specified v ol CC22ma table 12: absolute maximum ratings symbol parameter minimum maximum unit symbol v supply power supply voltage (all supplies) C0.3 4.5 v v supply i supply total power supply current C 200 ma i supply i gnd total ground current C 200 ma i gnd v in dc input voltage C0.3 v dd _io + 0.3 v v in v out dc output voltage C0.3 v dd _io + 0.3 v v out t stg 1 storage temperature C40 +85 c t stg 1 table 13: operating current consumption for parallel output v aa = v aa _pix = v dd _io = v dd _pll = 2.8v; v dd = 1.8v; pll enabled and pixclk = 74.25 mhz; t a = 25c; c load = 10pf condition symbol min typ max unit digital operating current parallel, streaming, full resolution 45 fps i dd 14555ma i/o digital operating current parallel, streaming, full resolution 45 fps i dd _io 50 1 Cma analog operating current parallel, streaming, full resolution 45 fps i aa 45 50 ma pixel supply current parallel, streaming, full resolution 45 fps i aa _pix 6 10 ma pll supply current parallel, stre aming, full resolution 45 fps i dd _pll 6 8 ma
mt9m021-mt9m031_ds rev. g pub. 4/15 en 22 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications hispi electrical specifications the on semiconductor mt9m021/mt9m031 sensor supports slvs mode only, and does not have a dll for timing adjustments. refer to the high-speed serial pixel (hispi) interface physical layer specification v2.00.00 for electrical definiti ons, specifications, and timing information. the v dd _slvs supply in this datasheet corresponds to v dd _tx in the hispi physical layer specification. similarly, v dd is equivalent to v dd _hispi as referenced in the specification. the hispi transmitter electrical specifications are listed at 700 mhz. table 14: standby current consumption analog - v aa + v aa _pix + v dd _pll; digital - v dd + v dd _io; t a = 25c definition condition min typ max unit hard standby (clock off, driven low) analog, 2.8v C 3 10 ? a digital, 1.8v C 8 75 ? a hard standby (clock on, extclk = 20 mhz) analog, 2.8v C 12 20 ? a digital, 1.8v C 0.87 1.3 ma soft standby (clock off, driven low) analog, 2.8v C 3 10 ? a digital, 1.8v C 8 75 ? a soft standby (clock on, extclk = 20 mhz) analog, 2.8v C 12 20 ? a digital, 1.8v C 0.87 1.3 ma table 15: input voltage and current (hispi power supply 0.4 v) measurement conditions: max freq 700 mhz parameter symbol min typ max unit supply current ( pwr hispi) (driving 100 ? load) i dd _slvs C 10 15 ma hispi common mode voltage (driving 100 ? load) v cmd v dd _slvs x 0.45 v dd _slvs/2 v dd _slvs x 0.55 v hispi differential output voltage (driving 100 ? load) |v od |v dd _slvs x 0.36 v dd _slvs/2 v dd _slvs x 0.64 v change in v cm between logic 1 and 0 ? v cm 25 mv change in |v od | between logic 1 and 0 |v od |25mv vod noise margin nm C 30 % difference in v cm between any two channels | ? v cm |50mv difference in v od between any two channels | ? v od |100mv common-mode ac voltage (pk) without v cm cap termination ? v cm _ac 50 mv common-mode ac voltage (pk) with v cm cap termination ? v cm _ac 30 mv max overshoot peak |v od |v od _ac 1.3 x |v od |v max overshoot vdiff pk-pk v diff_pkpk 2.6 x |v od |v eye height v eye 1.4 x v od single-ended output impedance ro 35 50 70 ? output impedance mismatch ? ro 20 %
mt9m021-mt9m031_ds rev. g pub. 4/15 en 23 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications figure 8: differential output voltage for clock or data pairs notes: 1. one ui is defined as the normalized mean ti me between one edge and the following edge of the clock. 2. taken from 0v crossing point w/ dll off. 3. also defined with a maximum loading capacitance of 10pf on any pin. the loading capacitance may also need to be less for higher bitrates so the rise and fall times do not exceed the maximum 0.3ui. 4. the absolute mean skew between the clock lane and any data lane in the same phy between any edges. 5. the absolute mean skew between any clock in one phy and any data lane in any other phy between any edges. 6. differential skew is defined as the skew between complementary outputs. it is measured as the absolute time between the two complementary edges at mean v cm point. table 16: rise and fall times measurement conditions: hispi powe r supply 0.4v, max freq 700 mhz parameter symbol min typ max unit data rate 1/ui 280 C 700 mb/s max setup time from transmitter txpre 0.3 C C ui 1 max hold time from transmitter txpost 0.3 C C ui rise time (20% - 80%) rise C 0.25ui C fall time (20% - 80%) fall 150ps 0.25 ui C clock duty pll_duty 45 50 55 % bitrate period t pw 1.43 3.57 ns 1 eye width t eye 0.3 ui 1, 2 data total jitter (pk pk)@1e-9 t totaljit 0.2 ui 1, 2 clock period jitter(rms) t ckjit 50 ps 2 clock cycle to cycle jitter (rms) t cyjit 100 ps 2 clock to data skew t chskew -0.1 0.1 ui 1, 2 phy-to-phy skew t |physkew| 2.1 ui 1, 5 mean diferential skew t diffskew C100 100 ps 6 0v diff) vdiffmax vdiffmin output signal is 'cp - cn' or 'dp - dn'
mt9m021-mt9m031_ds rev. g pub. 4/15 en 24 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor electrical specifications figure 9: eye diagram for clock and data signals figure 10: skew within the phy and output channels clkjitter t rigger/ reference vdiff max vdiff ui/ 2 ui/ 2 vdiff txpre txpost clock mask data mask rise fall 20% 80% tcmpskew vcmd tc hskew1phy
mt9m021-mt9m031_ds rev. g pub. 4/15 en 25 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor power-on reset and standby timing power-on reset and standby timing power-up sequence the recommended power-up sequence for the mt9m021/mt9m031 is shown in figure 11. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. turn on v dd _pll power supply. 2. after 0?10 ? s, turn on v aa and v aa _pix power supply. 3. after 0?10 ? s, turn on v dd _io power supply. 4. after the last power supply is stable, enable extclk. 5. assert reset_bar for at least 1ms. 6. wait 150000 extclks (for internal initialization into software standby. 7. configure pll, output, and image settings to desired values. 8. wait 1ms for the pll to lock. 9. set streaming mode (r0x301a[2] = 1). figure 11: power up notes: 1. xtal settling time is component-de pendent, usually taking about 10 C 100 ms. 2. hard reset time is the minimum time required after power rails are settled. in a circuit where hard reset is held down by rc circuit, then the rc ti me must include the all power rail settle time and xtal settle time. 3. it is critical that v dd _pll is not powered up after the other power supplies. it must be powered before or at least at the same time as the others. if the case happens that v dd _pll is powered after table 17: power-up sequence definition symbol minimum typical maximum unit v dd _pll to v aa /v aa _pix t0 0 10 C ? s v aa /v aa _pix to v dd _io t1 0 10 C ? s v dd _io to v dd t2 0 10 C ? s v dd to v dd _slvs t3 0 10 C ? s xtal settle time tx C 30 1 Cms hard reset t4 1 2 CC ms internal initializat ion t5 150000 C C extclks pll lock time t6 1 C C ms v dd _pll (2.8) v aa _pix v aa (2.8) v dd _io (1.8/2.8) v dd (1.8) v dd _slvs (0.4) extclk reset_b t0 t1 t2 t3 tx t4 t5 t6 hard reset internal initialization software standby pll lock streaming
mt9m021-mt9m031_ds rev. g pub. 4/15 en 26 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor power-on reset and standby timing other supplies then the sensor may have functionalit y issues and will experience high current draw on this supply. power-down sequence the recommended power-down sequence for the mt9m021/mt9m031 is shown in figure 12. the available power supplies (v dd _io, v dd , v dd _slvs, v dd _pll, v aa , v aa _pix) must have the separation specified below. 1. disable streaming if output is acti ve by setting standby r0x301a[2] = 0 2. the soft standby state is reached after the current row or frame, depending on config- uration, has ended. 3. turn off v dd _slvs. 4. turn off v dd . 5. turn off v dd _io 6. turn off v aa /v aa _pix. 7. turn off v dd _pll. figure 12: power down table 18: power-down sequence definition symbol minimum typical maximum unit v dd _slvs to v dd t0 0 C C ? s v dd to v dd _io t1 0 C C ? s v dd _io to v aa /v aa _pix t2 0 C C ? s v aa /v aa _pix to v dd _pll t3 0 C C ? s v dd _io (1.8/2.8) t4 t 0 t1 t3 t2 extclk v dd _slvs (0.4) v dd (1.8) v aa _pix v aa (2.8) v dd _pll (2.8) power down until next power up cycle
mt9m021-mt9m031_ds rev. g pub. 4/15 en 27 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor power-on reset and standby timing note: t4 is required between power down and next po wer up time; all decoupling caps from regulators must be completely discharged. pwrdn until next pwrup time t4 100 C C ms table 18: power-down sequence definition symbol minimum typical maximum unit
mt9m021-mt9m031_ds rev. g pub. 4/15 en 28 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor power-on reset and standby timing figure 13: quantum efficiency C monochrome sensor 0 10 20 30 40 50 60 70 80 350 450 550 650 750 850 950 1050 1150 quantum efficiency (%) wavelength (nm)
mt9m021-mt9m031_ds rev. g pub. 4/15 en 29 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor power-on reset and standby timing figure 14: quantum efficiency C color sensor
mt9m021-mt9m031_ds rev. g pub. 4/15 en 30 ?semiconductor components industries, llc,2015 mt9m021/mt9m031: 1/3-inch cmos digital image sensor package dimensions package dimensions figure 15: 64-ball ibga package outline drawing note: all dimensions in millimeters.
mt9m021-mt9m031_ds rev. g pub. 4/15 en 31 ?semiconductor components industries, llc,2015 mt9m021/mt9m031: 1/3-inch cmos digital image sensor package dimensions figure 16: 48-pin ilcc package drawing
mt9m021-mt9m031_ds rev. g pub. 4/15 en 32 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor revision history revision history rev. g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4/15/15 ? updated ?ordering information? on page 2 rev. f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/4/12 ? converted to on semiconductor template ? removed confidential marking rev. e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/4/12 ? updated to production ? updated table 1, ?key parameters,? on page 1 ? updated table 2, ?available part numbers,? on page 2 ? updated ?general description? on page 8 ? updated figure 2: ?typical configuratio n: serial four-lane hispi interface,? on page 10 ? updated figure 3: ?typical configuration: parallel pixel data interface,? on page 11 ? updated table 5, ?two-wire serial bus characteristics,? on page 17 ? updated figure 7: ?i/o timing diagram,? on page 18 ? updated table 6, ?i/o timing characteristics1,? on page 18 ? added table 7, i/o rise slew rate (2.8v vdd_io)1 and table 8, ?i/o fall slew rate (2.8v vdd_io)1,? on page 20 ? added table 9, i/o rise slew rate (1.8v vdd_io)1 and table 10, ?i/o fall slew rate (1.8v vdd_io)1,? on page 20 ? updated table 13, ?operating current consumption for parallel output,? on page 21 ? updated table 14, ?standby current consumption,? on page 22 rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5/17/12 ? added mt9m031 ? updated table 1, ?key parameters,? on page 1 ? updated table 2, ?available part numbers,? on page 2 ? updated ?lv format options? on page 14 ? updated ?hispi physical layer? on page 15 ? added figure 5: ?48 ilcc package, parallel output,? on page 14 ? added table 4, ?pin descriptions - 48 ilcc package, parallel,? on page 15 ? updated figure 7: ?i/o timing diagram,? on page 18 ? updated table 6, ?i/o timing characteristics1,? on page 18 ? updated ?hispi electrical specifications? on page 22 ? added table 15, ?input voltage and current (hispi power supply 0.4 v),? on page 22 ? added figure 8: ?differential output voltage for clock or data pairs,? on page 23 ? added table 16, ?rise and fall times,? on page 23 ? added figure 9: ?eye diagram for clock and data signals,? on page 24 ? added figure 10: ?skew within the phy and output channels,? on page 24 ? added figure 16: ?48-pin ilcc package drawing,? on page 31 ? deleted the following major sections and their sub-sections. refer to the developer guide: ?pixel data format ?output data format ? two-wire serial register interface
mt9m021-mt9m031_ds rev. g pub. 4/15 en 33 ?semiconductor components industries, llc,2015. mt9m021/mt9m031: 1/3-inch cmos digital image sensor revision history ?real-time context switching ? replaced ?feature description? with ?functional overview? on page 8 and ?features overview? on page 9 rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/14/11 ? updated to preliminary ? updated operating temperature in table 1, ?key parameters,? on page 1 and in ?general description? on page 8 ? updated figure 6: ?two-wire serial bus timing parameters,? on page 16 ? updated table 5, ?two-wire serial bus characteristics,? on page 17 ? updated figure 7: ?i/o timing diagram,? on page 18 ? added table 6, ?i/o timing characteristics1,? on page 18 ? updated table 6, ?dc electrical characteristics,? on page 14 ? replaced table 10, power consumption with table 13, ?operating current consump- tion for parallel output,? on page 21 ? added table 14, ?standby current consumption,? on page 22 ? updated table 14, power supply and operating temperatures ? deleted table 14, ?input voltage and current,? on page 39 ? added table 15, ?slvs electrical dc specification,? on page 40 ? updated table 16, ?slvs electrical timing specification,? on page 40 ? updated table 17, ?power-up sequence,? on page 25 ? updated figure 13: ?quantum efficiency ? monochrome sensor,? on page 28 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/16/09 ? updated the following parameters in table 1, ?key parameters,? on page 1 ? input clock range ?responsivity ?dynamic range ? updated table 2, ?available part numbers,? on page 2 ? replaced ?scaling? with ?digital binning? in third paragraph of ?general description? on page 8 ? updated master clock range in figure 2 on page 10 and figure 3 on page 11 ? updated number of rows in first sentence of first paragraph in ?pixel array structure? on page 10 ? updated array pixel coordinates in figure 6 on page 12 ? added ?default readout order? on page 12 ? updated ?output data format? on page 13 ? added ?readout sequence? on page 13 ? replaced ?parallel data timing? section with ?parallel output data timing? on page 14 ? moved figure 13, line timing and fram e_valid/line_valid signals and table 5, frame time: long integration time to ne w section ?frame time? on page 17; added table 4, ?frame time (example based on 1280 x 960, 45 frames per second),? on page 17 ? updated first paragraph of ?real-time context switching? on page 19 ? updated table 6, ?real-time context-switchable registers,? on page 19 ? updated ?features? section as follows: ? updated ?trigger mode? on page 20 ? moved ?hard reset of logic? and soft reset of logic? to ?reset? on page 21
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9m021/mt9m031: 1/3-inch cmos digital image sensor revision history mt9m021-mt9m031_ds rev. g pub. 4/15 en 34 ?semiconductor components industries, llc,2015 . ? added ?readout modes? on page 25; ?mirro r? on page 27, ?maintaining a constant frame rate? on page 28, ?synchronizing register writes to frame boundaries? on page 28; ?restart? on page 29, ?automatic exposure control? on page 29,and ?test patterns? on page 32 ? deleted ?pixel integration control,? ?pixel clock speed,? ?statistics and settings readout,? ?read mode options,? and ?line_valid? ? updated ?electrical specifications? on page 16 ? moved ?power-on reset and standby timing? on page 25 from appendix to main body of document ? replaced figure 13: ?quantum efficiency ? monochrome sensor,? on page 28 with placeholder ? updated figure 15: ?64-ball ibga package outline drawing,? on page 30 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2/18/09 ?initial release

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